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A4016U4X
WCMA4016U4X
256K x 16 Static RAM
Features
* Low Voltage range: -- 2.7V-3.3V * Ultra-low active power -- Typical active current: 1.5 mA @ f = 1MHz * * * * -- Typical active current: 7 mA @ f = fmax Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The WCMA4016U4X is available in a 48-ball FBGA package.
Functional Description
The WCMA4016U4X is a high-performance CMOS static RAMs organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This device is ideal for portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array 2048 x 2048
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER BHE WE CE OE BLE
A11 A12
A13 A14 A15 A16 CE
Pow er Down Circuit
BHE BLE
A17
WCMA4016U4X
Pin Configuration[1, 2]
FBGA (Top View) 4 5 3 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC
2 OE
6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H
BHE I/O10 I/O11
I/O12 DNU I/O13 NC A8 A14 A12 A9
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ...-0.5V to Vccmax + 0.5V DC Voltage Applied to Outputs in High Z State[3] ....................................-0.5V to VCC + 0.3V DC Input Voltage[3]..................................-0.5V to VCC + 0.3V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Device WCMA4016U4X Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.3V
Product Portfolio
Power Dissipation (Industrial) Product VCC Range VCC(min.) VCC(typ.)[4] VCC(max.) WCMA4016U4X 2.7V 3.0V 3.3V 70 ns Speed Operating, ICC f = 1 MHz Typ.[4] 1.5 mA Max. 3 mA f = fmax Typ.[4] 7 mA Max. 15 mA Standby (ISB2) Typ.[4] 7 A Max. 15 A
Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or Vss to ensure proper application. 3. VIL(min.) = -2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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WCMA4016U4X
WCMA4016U4X Parameter VOH VOL VIH VIL IIX IOZ Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC
f = 1 MHz
Test Conditions IOH = -1.0 mA IOL = 2.1mA VCC = 2.7V VCC = 2.7V
Min. 2.4
Typ.[4]
Max. 0.4
Unit V V V V A A
2.2 -0.3 -1 -1 7 1.5
VCC + 0.3V 0.8 +1 +1 15 3
ICC
VCC = 3.3V IOUT = 0 mA CMOS Levels
mA
ISB1
CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, Vcc=3.3V
7
15
A
ISB2
.
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF
Thermal Resistance
Description Thermal Resistance (Junction to Ambient)[5] Thermal Resistance (Junction to Case)[5]
Note: 5. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board
Symbol JA JC
BGA 55 16
Units C/W C/W
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WCMA4016U4X
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2
VCC Typ 10% GND Rise TIme: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
3.0V 1.105 1.550 0.645 1.75V
Unit KOhms KOhms KOhms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[5] tR[6] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= 1.5V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 3 Typ.[4] Max. Vccmax 10 Unit V A ns ns
Data Retention Waveform[7]
DATA RETENTION MODE VCC CE or BHE.BLE
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
Note: 6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100s or stable at VCC(min.) >100 s. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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WCMA4016U4X
Switching Characteristics Over the Operating Range[8]
70 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[10] tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[12]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[9] [9, 11]
Min 70
Max
Unit ns
70 10 70 35 5 25 10 25 0 70 70 5 25 70 60 60 0 0 50 60 30 0 25 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z
[9]
CE HIGH to High Z[9, 11] CE LOW to Power-Up CE HIGH to Power-Down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z[9] BHE / BLE HIGH to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BHE / BLE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[9, 11] WE HIGH to Low Z[9]
[9, 11]
Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10ns 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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WCMA4016U4X
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)
[14, 15]
ADDRESS
CE tACE OE tDOE BHE/BLE tLZOE
tRC tPD tHZCE
tHZOE
tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 13. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
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WCMA4016U4X
Switching Waveforms (continued)
[12, 16, 17]
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS tSCE CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 18 tHZOE
[12, 16, 17]
tHD
DATAIN VALID
Write Cycle No. 2 (CE Controlled)
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied.
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WCMA4016U4X
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[17]
tWC ADDRESS tSCE CE
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATAI/O NOTE 18 tHZWE DATAIN VALID
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[17]
tWC ADDRESS
CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O NOTE 18 DATAIN VALID tHD tBW tHA
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WCMA4016U4X
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.)
Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage
14.0 12.0 ICC (mA) ISB (A) 10.0 8.0 6.0 4.0 2.0 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) (f = 1 MHz) (f = fmax) 12.0 10.0 8.0
Access Time vs. Supply Voltage
60 50 40 TAA (ns) 30 20 10 0
6.0 4.0 2.0 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V)
2.7
3.0
3.3
SUPPLY VOLTAGE (V)
Truth Table
CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0-I/O7 in High Z Mode Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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WCMA4016U4X
Ordering Information
Speed (ns) 70 Ordering Code WCMA4016U4X-FF70 Package Name FB48A Package Type 48-Ball Fine Pitch BGA Operating Range Industrial
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WCMA4016U4X
Package Diagrams 48-Ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA, FB48A
Top View Bottom View
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WCMA4016U4X
Document Title: WCMA4016U4X 256K x 16 STATIC RAM REV. ** Spec # 38-14013 ECN # 115230 Issue Date 4/24/2002 Orig. of Change MGN Description of Change New Datasheet
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